1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a device for reducing/minimizing a test time of a test operation in a semiconductor memory device including a repair circuit for repairing defective memory cells.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a normal cell array 110, a redundancy cell array 120, a column fuse block 130, a comparison block 140, a control block 150, a normal decoder 160, and a redundancy decoder 170.
The normal cell array 110 includes a plurality of memory cells which are disposed at each intersection of a plurality of row lines (not shown) and a plurality of column lines, respectively corresponding to a row address (not shown) and a column address YA.
The redundancy cell array 120 includes a plurality of memory cells for replacing defective memory cells.
The normal cell array 110 includes normal column lines corresponding to a plurality of normal column select signals NYI1 and NYI2, and the redundancy cell array 120 includes redundancy column lines corresponding to a plurality of redundancy column select signals RYI.
The column fuse block 130 includes a plurality of fuse sets, and outputs a fuse set enable signal YREN indicating that a defective unit cell exists among a plurality of unit cells and a repair address YRA for replacing a column address corresponding to the defective unit cell among the plurality of unit cells.
The comparison block 140 receives the fuse set enable signal YREN and the repair address YRA from the column fuse block 130 and receives the column address YA from outside. When the fuse set enable signal YREN is enabled, the comparison block 140 may compare the column address YA with the repair address YRA and output a column repair signal SYEB based on a comparison result. The column repair signal SYEB may indicate that a repair operation is necessary when the column address YA inputted from the outside corresponds to the defective unit cell.
The control block 150 may generate a normal column enable signal NCE for controlling the normal column line, in response to the column repair signal SYEB. The control block 150 disables the normal column enable signal NCE if the column repair signal SYEB is enabled.
The normal decoder 160 receives the column address YA, a mode control signal TM, and the normal column enable signal NCE. The semiconductor memory device performs a normal operation a first operation mode in which the mode control signal TM is disabled. Further, the semiconductor memory device performs a test operation by driving, not a single column line, but double column lines in a second operation mode in which the mode control signal TM is enabled.
The normal decoder 160 decodes the column address YA and enables the normal column select signals NYI1 and NYI2 when the normal column enable signal NCE is enabled in the first operation mode. The normal cell array 110 drives the normal column line corresponding to the normal column select signals NYI1 and NYI2.
The normal decoder 160 stops a decoding operation on the column address YA when the normal column enable signal NCE is disabled in the first operation mode.
The normal decoder 160 retains a most significant bit of the column address YA to a floating state, and decodes the column address YA and outputs the normal column select signals NYI1 and NYI2, when the normal column enable signal NCE is enabled in the second operation mode. Because the normal decoder 160 retains the most significant bit of the column address YA to the floating state, the normal column lines to be finally enabled may be first and second normal column lines corresponding to column addresses YA which are different in terms of only their most significant bits.
The normal decoder 160 stops the decoding operation on the column address YA when the normal column enable signal NCE is disabled in the second operation mode.
The redundancy decoder 170 receives and decodes the column repair signal SYEB, and enables the redundancy column select signal RYI corresponding to the column repair signal SYEB. The redundancy cell array 120 drives the redundancy column line corresponding to the enabled redundancy column select signal RYI.
Next, describing operations, the mode control signal TM is disabled in the first operation mode. The comparison block 140 receives the column address YA from the outside, receives the fuse set enable signal YREN and the repair address YRA outputted from the column fuse block 130, and compares the column address YA with the repair address YRA. When the column address YA is different from the repair address YRA, the column repair signal SYEB is disabled, and accordingly, the control block 150 enables the normal column enable signal NCE. The normal decoder 160 decodes the column address YA and outputs the normal column select signals NYI and NYI2. The normal cell array 110 drives the normal column line corresponding to the normal column select signals NYI1 and NYI2.
Conversely, when the column address YA is identical to the repair address YRA, the column repair signal SYEB is enabled. The redundancy decoder 170 may receive and decode the column repair signal SYEB, and output the redundancy column select signal RYI. The redundancy cell array 120 may enable the redundancy column line corresponding to the redundancy column select signal RYI. The control block 150, which receives the enabled column repair signal SYEB, disables the normal column enable signal NCE, and the normal decoder 160 stops the decoding operation in response to the disabled normal column enable signal NCE.
In the second operation mode, the mode control signal TM, which is enabled, is received by the normal decoder 160. The comparison block 140 receives the column address YA from the outside, receives the fuse set enable signal YREN and the repair address YRA outputted from the column fuse block 130, and compares the column address YA with the repair address YRA. When the column address YA is different from the repair address YRA, the column repair signal SYEB is disabled, and accordingly, the control block 150 enables the normal column enable signal NCE. The normal decoder 160 may retain the most significant bit of the column address YA in the floating state when the normal column enable signal NCE and the mode control signal TM are enabled, decode the received column address YA, and output the normal column select signals NYI1 and NYI2. The normal cell array 110 may enable the first and second normal column lines corresponding to the normal column select signals NYI1 and NYI2.
Conversely, when the column address YA is identical to the repair address YRA, the column repair signal SYEB is enabled. The redundancy decoder 170 may receive and decode the column repair signal SYEB, and output the redundancy column select signal RYI. The redundancy cell array 120 may enable the redundancy column line corresponding to the redundancy column select signal RYI. The control block 150, which receives the enabled column repair signal SYEB, disables the normal column enable signal NCE, and the normal decoder 160 stops the decoding operation in response to the disabled normal column enable signal NCE. That is, even when the mode control signal TM for the second operation mode is enabled, the normal decoder 160 may not perform the decoding operation since the normal column enable signal NCE is disabled.
When a fail does not occur in the first normal column line corresponding to the column address YA in the second operation mode in which a double column test operation is performed, a test operation may be performed by simultaneously enabling the first normal column line and the second normal column line. However, when a fail occurs in the first normal column line, a redundancy column line is enabled through a repair operation, and the second normal column line corresponding to the column address YA, which is different in terms of only the most significant bit thereof from the column address YA of the first normal column line, is disabled. Thus, in the second operation mode, when the repair operation is performed since a failure occurs in the first normal column line between the first and second normal column lines corresponding to the column addresses YA different in terms of only their most significant bits, a test operation may not be simultaneously performed on the remaining second normal column line.
In the conventional semiconductor memory device, when a test operation is performed by enabling double normal column lines in a second operation mode, since the test operation is performed by enabling not double column lines but only a redundancy column line after a repair operation, a time required for the test operation is lengthened.